FPGA · Verilog HDL
UART AI Anomaly Detector
- Role
- Developer
- Context
- FPGA · Verilog HDL
Overview
An FPGA-based anomaly detection system for UART communication monitoring, using FIFO buffering. Designed at RTL level in Verilog HDL and verified with self-checking testbenches.
Stack
- FPGA
- Verilog
- RTL
- UART
- Anomaly Detection